Memory devices typically include a plurality of memory cells, which may be arranged in an array of intersecting rows and columns. Read and write operations, to respectively store and retrieve memory contents, may involve multiple steps and accessing multiple memory cells at approximately the same time. One or more clock signals can serve to synchronize activities in a memory device. Such clock signals can be distributed throughout the memory device through its clock distribution network. Various components of a clock path, for example clock drivers and delay cells of a delay line, can be sensitive to variations in supply voltage and/or current used to power the memory device. Clock path constituents can differ in their sensitivity to supply variations.
Memory devices are commonly powered by a variety of means. In some cases, the circuits are powered solely from an external source coupled to a power supply terminal. Memory device suppliers can specify minimum and maximum supply voltage and/or current (i.e., operating parameters) for proper operation of the memory device. Even within specified operating parameters, components of a clock path may exhibit different levels of sensitivity to supply variations sufficient to cause time variation (or jitter) of the clock signal and outputs.
Circuits in the clock path that include a chain of delay cells, for example, delay-lock loops, duty cycle correction circuits, and other delay circuits, may introduce significant jitter resulting from power supply variations because each delay cell may add a time variation. Whereas the jitter introduced by each delay cell may not be significant, the sum of the time variations contributed by all of the delay cells may be enough to cause problems in operation.
Accordingly, it is desirable to reduce clock jitter arising from variations in supply voltage and/or current.